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| author | onefang | 2021-09-02 17:05:51 +1000 |
|---|---|---|
| committer | onefang | 2021-09-02 17:05:51 +1000 |
| commit | 0986c05e5e7f28b59a2cb81b29f63dbf71c39467 (patch) | |
| tree | c17781a5e1de2e29342142824833fad1e06ab9e0 /src | |
| parent | Comment++ (diff) | |
| download | opensim-SC-0986c05e5e7f28b59a2cb81b29f63dbf71c39467.zip opensim-SC-0986c05e5e7f28b59a2cb81b29f63dbf71c39467.tar.gz opensim-SC-0986c05e5e7f28b59a2cb81b29f63dbf71c39467.tar.bz2 opensim-SC-0986c05e5e7f28b59a2cb81b29f63dbf71c39467.tar.xz | |
Default config entry for port to start from.
Diffstat (limited to 'src')
| -rw-r--r-- | src/.sledjChisl.conf.lua | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/.sledjChisl.conf.lua b/src/.sledjChisl.conf.lua index e44886b..cede4e4 100644 --- a/src/.sledjChisl.conf.lua +++ b/src/.sledjChisl.conf.lua | |||
| @@ -16,7 +16,6 @@ config = | |||
| 16 | ["Tconsole"] = "SledjChisl"; | 16 | ["Tconsole"] = "SledjChisl"; |
| 17 | ["Tsocket"] = "opensim-tmux.socket"; | 17 | ["Tsocket"] = "opensim-tmux.socket"; |
| 18 | ["Ttab"] = "SC"; | 18 | ["Ttab"] = "SC"; |
| 19 | ["startPort"] = 8002; | ||
| 20 | ["loadAverageInc"] = 0.7; | 19 | ["loadAverageInc"] = 0.7; |
| 21 | ["simTimeOut"] = 45; -- seconds | 20 | ["simTimeOut"] = 45; -- seconds |
| 22 | ["bulkSims"] = 0; -- 0 means figure it out from number of CPUs. | 21 | ["bulkSims"] = 0; -- 0 means figure it out from number of CPUs. |