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| author | onefang | 2021-08-27 03:46:06 +1000 |
|---|---|---|
| committer | onefang | 2021-08-27 03:46:06 +1000 |
| commit | 2ed54a3817608bcf372b091efc9cb76a65150d33 (patch) | |
| tree | 9d2ea2ea554c5b79a250a9aafe077d275b7048a5 /src/.sledjChisl.conf.lua | |
| parent | Log directory and it's contents only readable / writable for the opensim user. (diff) | |
| download | opensim-SC-2ed54a3817608bcf372b091efc9cb76a65150d33.zip opensim-SC-2ed54a3817608bcf372b091efc9cb76a65150d33.tar.gz opensim-SC-2ed54a3817608bcf372b091efc9cb76a65150d33.tar.bz2 opensim-SC-2ed54a3817608bcf372b091efc9cb76a65150d33.tar.xz | |
Configure the base port number for sim autogenerated ports.
Diffstat (limited to 'src/.sledjChisl.conf.lua')
| -rw-r--r-- | src/.sledjChisl.conf.lua | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/.sledjChisl.conf.lua b/src/.sledjChisl.conf.lua index cede4e4..e44886b 100644 --- a/src/.sledjChisl.conf.lua +++ b/src/.sledjChisl.conf.lua | |||
| @@ -16,6 +16,7 @@ config = | |||
| 16 | ["Tconsole"] = "SledjChisl"; | 16 | ["Tconsole"] = "SledjChisl"; |
| 17 | ["Tsocket"] = "opensim-tmux.socket"; | 17 | ["Tsocket"] = "opensim-tmux.socket"; |
| 18 | ["Ttab"] = "SC"; | 18 | ["Ttab"] = "SC"; |
| 19 | ["startPort"] = 8002; | ||
| 19 | ["loadAverageInc"] = 0.7; | 20 | ["loadAverageInc"] = 0.7; |
| 20 | ["simTimeOut"] = 45; -- seconds | 21 | ["simTimeOut"] = 45; -- seconds |
| 21 | ["bulkSims"] = 0; -- 0 means figure it out from number of CPUs. | 22 | ["bulkSims"] = 0; -- 0 means figure it out from number of CPUs. |