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authorJacek Antonelli2008-08-15 23:44:59 -0500
committerJacek Antonelli2008-08-15 23:44:59 -0500
commita408bac29378072fbf36864164149458c978cfcc (patch)
tree67feccf1a5d3816611ba48d6762f86f0f7f4b1f6 /linden/indra/llcommon/llprocessor.cpp
parentSecond Life viewer sources 1.17.0.12 (diff)
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Second Life viewer sources 1.17.1.0
Diffstat (limited to 'linden/indra/llcommon/llprocessor.cpp')
-rw-r--r--linden/indra/llcommon/llprocessor.cpp12
1 files changed, 6 insertions, 6 deletions
diff --git a/linden/indra/llcommon/llprocessor.cpp b/linden/indra/llcommon/llprocessor.cpp
index 40dc00c..bd21351 100644
--- a/linden/indra/llcommon/llprocessor.cpp
+++ b/linden/indra/llcommon/llprocessor.cpp
@@ -453,7 +453,7 @@ bool CProcessor::AnalyzeIntelProcessor()
453 case 3: // Model = 8, Brand id = 3: Pentium III Xeon (on-die L2 cache) processor model 453 case 3: // Model = 8, Brand id = 3: Pentium III Xeon (on-die L2 cache) processor model
454 strncat(strCPUName, "Intel Pentium III Xeon (0.18 micron process) with internal L2 cache", sizeof(strCPUName)-(strlen(strCPUName)-1)); /*Flawfinder: ignore*/ 454 strncat(strCPUName, "Intel Pentium III Xeon (0.18 micron process) with internal L2 cache", sizeof(strCPUName)-(strlen(strCPUName)-1)); /*Flawfinder: ignore*/
455 break; 455 break;
456 default: // ...² 456 default: // ...
457 strncat(strCPUName, "Intel Pentium III core (unknown model, 0.18 micron process) with internal L2 cache", sizeof(strCPUName)-(strlen(strCPUName)-1)); /*Flawfinder: ignore*/ 457 strncat(strCPUName, "Intel Pentium III core (unknown model, 0.18 micron process) with internal L2 cache", sizeof(strCPUName)-(strlen(strCPUName)-1)); /*Flawfinder: ignore*/
458 break; 458 break;
459 } 459 }
@@ -664,8 +664,8 @@ bool CProcessor::AnalyzeAMDProcessor()
664 mov dword ptr [tmp+44], edx 664 mov dword ptr [tmp+44], edx
665 } 665 }
666 // And copy it to the brand id string 666 // And copy it to the brand id string
667 strncpy(CPUInfo.strBrandID, tmp,sizeof(CPUInfo.strBrandID-1)); /* Flawfinder: ignore */ 667 strncpy(CPUInfo.strBrandID, tmp,sizeof(CPUInfo.strBrandID)-1);
668 CPUInfo.strBrandID[sizeof(CPUInfo.strBrandID-1)]='\0'; 668 CPUInfo.strBrandID[sizeof(CPUInfo.strBrandID)-1]='\0';
669 } 669 }
670 else 670 else
671 { 671 {
@@ -1280,17 +1280,17 @@ void CProcessor::DecodeProcessorConfiguration(unsigned int cfg)
1280 CPUInfo._L1.Data.uiAssociativeWays = 4; 1280 CPUInfo._L1.Data.uiAssociativeWays = 4;
1281 CPUInfo._L1.Data.uiLineSize = 64; 1281 CPUInfo._L1.Data.uiLineSize = 64;
1282 break; 1282 break;
1283 case 0x70: // cfg = 0x70: trace L1 cache present, 12 KµOPs, 4 ways 1283 case 0x70: // cfg = 0x70: trace L1 cache present, 12 KuOPs, 4 ways
1284 CPUInfo._Trace.bPresent = true; 1284 CPUInfo._Trace.bPresent = true;
1285 strcpy(CPUInfo._Trace.strSize, "12 K-micro-ops"); /* Flawfinder: ignore */ 1285 strcpy(CPUInfo._Trace.strSize, "12 K-micro-ops"); /* Flawfinder: ignore */
1286 CPUInfo._Trace.uiAssociativeWays = 4; 1286 CPUInfo._Trace.uiAssociativeWays = 4;
1287 break; 1287 break;
1288 case 0x71: // cfg = 0x71: trace L1 cache present, 16 KµOPs, 4 ways 1288 case 0x71: // cfg = 0x71: trace L1 cache present, 16 KuOPs, 4 ways
1289 CPUInfo._Trace.bPresent = true; 1289 CPUInfo._Trace.bPresent = true;
1290 strcpy(CPUInfo._Trace.strSize, "16 K-micro-ops"); /* Flawfinder: ignore */ 1290 strcpy(CPUInfo._Trace.strSize, "16 K-micro-ops"); /* Flawfinder: ignore */
1291 CPUInfo._Trace.uiAssociativeWays = 4; 1291 CPUInfo._Trace.uiAssociativeWays = 4;
1292 break; 1292 break;
1293 case 0x72: // cfg = 0x72: trace L1 cache present, 32 KµOPs, 4 ways 1293 case 0x72: // cfg = 0x72: trace L1 cache present, 32 KuOPs, 4 ways
1294 CPUInfo._Trace.bPresent = true; 1294 CPUInfo._Trace.bPresent = true;
1295 strcpy(CPUInfo._Trace.strSize, "32 K-micro-ops"); /* Flawfinder: ignore */ 1295 strcpy(CPUInfo._Trace.strSize, "32 K-micro-ops"); /* Flawfinder: ignore */
1296 CPUInfo._Trace.uiAssociativeWays = 4; 1296 CPUInfo._Trace.uiAssociativeWays = 4;