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-rw-r--r-- | libraries/luajit-2.0/src/lj_target_x86.h | 337 |
1 files changed, 337 insertions, 0 deletions
diff --git a/libraries/luajit-2.0/src/lj_target_x86.h b/libraries/luajit-2.0/src/lj_target_x86.h new file mode 100644 index 0000000..593e7b0 --- /dev/null +++ b/libraries/luajit-2.0/src/lj_target_x86.h | |||
@@ -0,0 +1,337 @@ | |||
1 | /* | ||
2 | ** Definitions for x86 and x64 CPUs. | ||
3 | ** Copyright (C) 2005-2011 Mike Pall. See Copyright Notice in luajit.h | ||
4 | */ | ||
5 | |||
6 | #ifndef _LJ_TARGET_X86_H | ||
7 | #define _LJ_TARGET_X86_H | ||
8 | |||
9 | /* -- Registers IDs ------------------------------------------------------- */ | ||
10 | |||
11 | #if LJ_64 | ||
12 | #define GPRDEF(_) \ | ||
13 | _(EAX) _(ECX) _(EDX) _(EBX) _(ESP) _(EBP) _(ESI) _(EDI) \ | ||
14 | _(R8D) _(R9D) _(R10D) _(R11D) _(R12D) _(R13D) _(R14D) _(R15D) | ||
15 | #define FPRDEF(_) \ | ||
16 | _(XMM0) _(XMM1) _(XMM2) _(XMM3) _(XMM4) _(XMM5) _(XMM6) _(XMM7) \ | ||
17 | _(XMM8) _(XMM9) _(XMM10) _(XMM11) _(XMM12) _(XMM13) _(XMM14) _(XMM15) | ||
18 | #else | ||
19 | #define GPRDEF(_) \ | ||
20 | _(EAX) _(ECX) _(EDX) _(EBX) _(ESP) _(EBP) _(ESI) _(EDI) | ||
21 | #define FPRDEF(_) \ | ||
22 | _(XMM0) _(XMM1) _(XMM2) _(XMM3) _(XMM4) _(XMM5) _(XMM6) _(XMM7) | ||
23 | #endif | ||
24 | #define VRIDDEF(_) \ | ||
25 | _(MRM) | ||
26 | |||
27 | #define RIDENUM(name) RID_##name, | ||
28 | |||
29 | enum { | ||
30 | GPRDEF(RIDENUM) /* General-purpose registers (GPRs). */ | ||
31 | FPRDEF(RIDENUM) /* Floating-point registers (FPRs). */ | ||
32 | RID_MAX, | ||
33 | RID_MRM = RID_MAX, /* Pseudo-id for ModRM operand. */ | ||
34 | |||
35 | /* Calling conventions. */ | ||
36 | RID_RET = RID_EAX, | ||
37 | #if LJ_64 | ||
38 | RID_FPRET = RID_XMM0, | ||
39 | #else | ||
40 | RID_RETLO = RID_EAX, | ||
41 | RID_RETHI = RID_EDX, | ||
42 | #endif | ||
43 | |||
44 | /* These definitions must match with the *.dasc file(s): */ | ||
45 | RID_BASE = RID_EDX, /* Interpreter BASE. */ | ||
46 | #if LJ_64 && !LJ_ABI_WIN | ||
47 | RID_LPC = RID_EBX, /* Interpreter PC. */ | ||
48 | RID_DISPATCH = RID_R14D, /* Interpreter DISPATCH table. */ | ||
49 | #else | ||
50 | RID_LPC = RID_ESI, /* Interpreter PC. */ | ||
51 | RID_DISPATCH = RID_EBX, /* Interpreter DISPATCH table. */ | ||
52 | #endif | ||
53 | |||
54 | /* Register ranges [min, max) and number of registers. */ | ||
55 | RID_MIN_GPR = RID_EAX, | ||
56 | RID_MIN_FPR = RID_XMM0, | ||
57 | RID_MAX_GPR = RID_MIN_FPR, | ||
58 | RID_MAX_FPR = RID_MAX, | ||
59 | RID_NUM_GPR = RID_MAX_GPR - RID_MIN_GPR, | ||
60 | RID_NUM_FPR = RID_MAX_FPR - RID_MIN_FPR, | ||
61 | }; | ||
62 | |||
63 | /* -- Register sets ------------------------------------------------------- */ | ||
64 | |||
65 | /* Make use of all registers, except the stack pointer. */ | ||
66 | #define RSET_GPR (RSET_RANGE(RID_MIN_GPR, RID_MAX_GPR)-RID2RSET(RID_ESP)) | ||
67 | #define RSET_FPR (RSET_RANGE(RID_MIN_FPR, RID_MAX_FPR)) | ||
68 | #define RSET_ALL (RSET_GPR|RSET_FPR) | ||
69 | #define RSET_INIT RSET_ALL | ||
70 | |||
71 | #if LJ_64 | ||
72 | /* Note: this requires the use of FORCE_REX! */ | ||
73 | #define RSET_GPR8 RSET_GPR | ||
74 | #else | ||
75 | #define RSET_GPR8 (RSET_RANGE(RID_EAX, RID_EBX+1)) | ||
76 | #endif | ||
77 | |||
78 | /* ABI-specific register sets. */ | ||
79 | #define RSET_ACD (RID2RSET(RID_EAX)|RID2RSET(RID_ECX)|RID2RSET(RID_EDX)) | ||
80 | #if LJ_64 | ||
81 | #if LJ_ABI_WIN | ||
82 | /* Windows x64 ABI. */ | ||
83 | #define RSET_SCRATCH \ | ||
84 | (RSET_ACD|RSET_RANGE(RID_R8D, RID_R11D+1)|RSET_RANGE(RID_XMM0, RID_XMM5+1)) | ||
85 | #define REGARG_GPRS \ | ||
86 | (RID_ECX|((RID_EDX|((RID_R8D|(RID_R9D<<5))<<5))<<5)) | ||
87 | #define REGARG_NUMGPR 4 | ||
88 | #define REGARG_NUMFPR 4 | ||
89 | #define REGARG_FIRSTFPR RID_XMM0 | ||
90 | #define REGARG_LASTFPR RID_XMM3 | ||
91 | #define STACKARG_OFS (4*8) | ||
92 | #else | ||
93 | /* The rest of the civilized x64 world has a common ABI. */ | ||
94 | #define RSET_SCRATCH \ | ||
95 | (RSET_ACD|RSET_RANGE(RID_ESI, RID_R11D+1)|RSET_FPR) | ||
96 | #define REGARG_GPRS \ | ||
97 | (RID_EDI|((RID_ESI|((RID_EDX|((RID_ECX|((RID_R8D|(RID_R9D \ | ||
98 | <<5))<<5))<<5))<<5))<<5)) | ||
99 | #define REGARG_NUMGPR 6 | ||
100 | #define REGARG_NUMFPR 8 | ||
101 | #define REGARG_FIRSTFPR RID_XMM0 | ||
102 | #define REGARG_LASTFPR RID_XMM7 | ||
103 | #define STACKARG_OFS 0 | ||
104 | #endif | ||
105 | #else | ||
106 | /* Common x86 ABI. */ | ||
107 | #define RSET_SCRATCH (RSET_ACD|RSET_FPR) | ||
108 | #define REGARG_GPRS (RID_ECX|(RID_EDX<<5)) /* Fastcall only. */ | ||
109 | #define REGARG_NUMGPR 2 /* Fastcall only. */ | ||
110 | #define REGARG_NUMFPR 0 | ||
111 | #define STACKARG_OFS 0 | ||
112 | #endif | ||
113 | |||
114 | #if LJ_64 | ||
115 | /* Prefer the low 8 regs of each type to reduce REX prefixes. */ | ||
116 | #undef rset_picktop | ||
117 | #define rset_picktop(rs) (lj_fls(lj_bswap(rs)) ^ 0x18) | ||
118 | #endif | ||
119 | |||
120 | /* -- Spill slots --------------------------------------------------------- */ | ||
121 | |||
122 | /* Spill slots are 32 bit wide. An even/odd pair is used for FPRs. | ||
123 | ** | ||
124 | ** SPS_FIXED: Available fixed spill slots in interpreter frame. | ||
125 | ** This definition must match with the *.dasc file(s). | ||
126 | ** | ||
127 | ** SPS_FIRST: First spill slot for general use. Reserve min. two 32 bit slots. | ||
128 | */ | ||
129 | #if LJ_64 | ||
130 | #if LJ_ABI_WIN | ||
131 | #define SPS_FIXED (4*2) | ||
132 | #define SPS_FIRST (4*2) /* Don't use callee register save area. */ | ||
133 | #else | ||
134 | #define SPS_FIXED 4 | ||
135 | #define SPS_FIRST 2 | ||
136 | #endif | ||
137 | #else | ||
138 | #define SPS_FIXED 6 | ||
139 | #define SPS_FIRST 2 | ||
140 | #endif | ||
141 | |||
142 | #define sps_scale(slot) (4 * (int32_t)(slot)) | ||
143 | #define sps_align(slot) (((slot) - SPS_FIXED + 3) & ~3) | ||
144 | |||
145 | /* -- Exit state ---------------------------------------------------------- */ | ||
146 | |||
147 | /* This definition must match with the *.dasc file(s). */ | ||
148 | typedef struct { | ||
149 | lua_Number fpr[RID_NUM_FPR]; /* Floating-point registers. */ | ||
150 | intptr_t gpr[RID_NUM_GPR]; /* General-purpose registers. */ | ||
151 | int32_t spill[256]; /* Spill slots. */ | ||
152 | } ExitState; | ||
153 | |||
154 | /* Limited by the range of a short fwd jump (127): (2+2)*(32-1)-2 = 122. */ | ||
155 | #define EXITSTUB_SPACING (2+2) | ||
156 | #define EXITSTUBS_PER_GROUP 32 | ||
157 | |||
158 | /* -- x86 ModRM operand encoding ------------------------------------------ */ | ||
159 | |||
160 | typedef enum { | ||
161 | XM_OFS0 = 0x00, XM_OFS8 = 0x40, XM_OFS32 = 0x80, XM_REG = 0xc0, | ||
162 | XM_SCALE1 = 0x00, XM_SCALE2 = 0x40, XM_SCALE4 = 0x80, XM_SCALE8 = 0xc0, | ||
163 | XM_MASK = 0xc0 | ||
164 | } x86Mode; | ||
165 | |||
166 | /* Structure to hold variable ModRM operand. */ | ||
167 | typedef struct { | ||
168 | int32_t ofs; /* Offset. */ | ||
169 | uint8_t base; /* Base register or RID_NONE. */ | ||
170 | uint8_t idx; /* Index register or RID_NONE. */ | ||
171 | uint8_t scale; /* Index scale (XM_SCALE1 .. XM_SCALE8). */ | ||
172 | } x86ModRM; | ||
173 | |||
174 | /* -- Opcodes ------------------------------------------------------------- */ | ||
175 | |||
176 | /* Macros to construct variable-length x86 opcodes. -(len+1) is in LSB. */ | ||
177 | #define XO_(o) ((uint32_t)(0x0000fe + (0x##o<<24))) | ||
178 | #define XO_FPU(a,b) ((uint32_t)(0x00fd + (0x##a<<16)+(0x##b<<24))) | ||
179 | #define XO_0f(o) ((uint32_t)(0x0f00fd + (0x##o<<24))) | ||
180 | #define XO_66(o) ((uint32_t)(0x6600fd + (0x##o<<24))) | ||
181 | #define XO_660f(o) ((uint32_t)(0x0f66fc + (0x##o<<24))) | ||
182 | #define XO_f20f(o) ((uint32_t)(0x0ff2fc + (0x##o<<24))) | ||
183 | #define XO_f30f(o) ((uint32_t)(0x0ff3fc + (0x##o<<24))) | ||
184 | |||
185 | /* This list of x86 opcodes is not intended to be complete. Opcodes are only | ||
186 | ** included when needed. Take a look at DynASM or jit.dis_x86 to see the | ||
187 | ** whole mess. | ||
188 | */ | ||
189 | typedef enum { | ||
190 | /* Fixed length opcodes. XI_* prefix. */ | ||
191 | XI_NOP = 0x90, | ||
192 | XI_CALL = 0xe8, | ||
193 | XI_JMP = 0xe9, | ||
194 | XI_JMPs = 0xeb, | ||
195 | XI_PUSH = 0x50, /* Really 50+r. */ | ||
196 | XI_JCCs = 0x70, /* Really 7x. */ | ||
197 | XI_JCCn = 0x80, /* Really 0f8x. */ | ||
198 | XI_LEA = 0x8d, | ||
199 | XI_MOVrib = 0xb0, /* Really b0+r. */ | ||
200 | XI_MOVri = 0xb8, /* Really b8+r. */ | ||
201 | XI_ARITHib = 0x80, | ||
202 | XI_ARITHi = 0x81, | ||
203 | XI_ARITHi8 = 0x83, | ||
204 | XI_PUSHi8 = 0x6a, | ||
205 | XI_TEST = 0x85, | ||
206 | XI_MOVmi = 0xc7, | ||
207 | XI_GROUP5 = 0xff, | ||
208 | |||
209 | /* Note: little-endian byte-order! */ | ||
210 | XI_FLDZ = 0xeed9, | ||
211 | XI_FLD1 = 0xe8d9, | ||
212 | XI_FLDLG2 = 0xecd9, | ||
213 | XI_FLDLN2 = 0xedd9, | ||
214 | XI_FDUP = 0xc0d9, /* Really fld st0. */ | ||
215 | XI_FPOP = 0xd8dd, /* Really fstp st0. */ | ||
216 | XI_FPOP1 = 0xd9dd, /* Really fstp st1. */ | ||
217 | XI_FRNDINT = 0xfcd9, | ||
218 | XI_FSIN = 0xfed9, | ||
219 | XI_FCOS = 0xffd9, | ||
220 | XI_FPTAN = 0xf2d9, | ||
221 | XI_FPATAN = 0xf3d9, | ||
222 | XI_FSCALE = 0xfdd9, | ||
223 | XI_FYL2X = 0xf1d9, | ||
224 | |||
225 | /* Variable-length opcodes. XO_* prefix. */ | ||
226 | XO_MOV = XO_(8b), | ||
227 | XO_MOVto = XO_(89), | ||
228 | XO_MOVtow = XO_66(89), | ||
229 | XO_MOVtob = XO_(88), | ||
230 | XO_MOVmi = XO_(c7), | ||
231 | XO_MOVmib = XO_(c6), | ||
232 | XO_LEA = XO_(8d), | ||
233 | XO_ARITHib = XO_(80), | ||
234 | XO_ARITHi = XO_(81), | ||
235 | XO_ARITHi8 = XO_(83), | ||
236 | XO_ARITHiw8 = XO_66(83), | ||
237 | XO_SHIFTi = XO_(c1), | ||
238 | XO_SHIFT1 = XO_(d1), | ||
239 | XO_SHIFTcl = XO_(d3), | ||
240 | XO_IMUL = XO_0f(af), | ||
241 | XO_IMULi = XO_(69), | ||
242 | XO_IMULi8 = XO_(6b), | ||
243 | XO_CMP = XO_(3b), | ||
244 | XO_TEST = XO_(85), | ||
245 | XO_GROUP3b = XO_(f6), | ||
246 | XO_GROUP3 = XO_(f7), | ||
247 | XO_GROUP5b = XO_(fe), | ||
248 | XO_GROUP5 = XO_(ff), | ||
249 | XO_MOVZXb = XO_0f(b6), | ||
250 | XO_MOVZXw = XO_0f(b7), | ||
251 | XO_MOVSXb = XO_0f(be), | ||
252 | XO_MOVSXw = XO_0f(bf), | ||
253 | XO_MOVSXd = XO_(63), | ||
254 | XO_BSWAP = XO_0f(c8), | ||
255 | XO_CMOV = XO_0f(40), | ||
256 | |||
257 | XO_MOVSD = XO_f20f(10), | ||
258 | XO_MOVSDto = XO_f20f(11), | ||
259 | XO_MOVSS = XO_f30f(10), | ||
260 | XO_MOVSSto = XO_f30f(11), | ||
261 | XO_MOVLPD = XO_660f(12), | ||
262 | XO_MOVAPS = XO_0f(28), | ||
263 | XO_XORPS = XO_0f(57), | ||
264 | XO_ANDPS = XO_0f(54), | ||
265 | XO_ADDSD = XO_f20f(58), | ||
266 | XO_SUBSD = XO_f20f(5c), | ||
267 | XO_MULSD = XO_f20f(59), | ||
268 | XO_DIVSD = XO_f20f(5e), | ||
269 | XO_SQRTSD = XO_f20f(51), | ||
270 | XO_MINSD = XO_f20f(5d), | ||
271 | XO_MAXSD = XO_f20f(5f), | ||
272 | XO_ROUNDSD = 0x0b3a0ffc, /* Really 66 0f 3a 0b. See asm_fpmath. */ | ||
273 | XO_UCOMISD = XO_660f(2e), | ||
274 | XO_CVTSI2SD = XO_f20f(2a), | ||
275 | XO_CVTSD2SI = XO_f20f(2d), | ||
276 | XO_CVTTSD2SI= XO_f20f(2c), | ||
277 | XO_CVTSI2SS = XO_f30f(2a), | ||
278 | XO_CVTSS2SI = XO_f30f(2d), | ||
279 | XO_CVTTSS2SI= XO_f30f(2c), | ||
280 | XO_CVTSS2SD = XO_f30f(5a), | ||
281 | XO_CVTSD2SS = XO_f20f(5a), | ||
282 | XO_ADDSS = XO_f30f(58), | ||
283 | XO_MOVD = XO_660f(6e), | ||
284 | XO_MOVDto = XO_660f(7e), | ||
285 | |||
286 | XO_FLDd = XO_(d9), XOg_FLDd = 0, | ||
287 | XO_FLDq = XO_(dd), XOg_FLDq = 0, | ||
288 | XO_FILDd = XO_(db), XOg_FILDd = 0, | ||
289 | XO_FILDq = XO_(df), XOg_FILDq = 5, | ||
290 | XO_FSTPd = XO_(d9), XOg_FSTPd = 3, | ||
291 | XO_FSTPq = XO_(dd), XOg_FSTPq = 3, | ||
292 | XO_FISTPq = XO_(df), XOg_FISTPq = 7, | ||
293 | XO_FISTTPq = XO_(dd), XOg_FISTTPq = 1, | ||
294 | XO_FADDq = XO_(dc), XOg_FADDq = 0, | ||
295 | XO_FLDCW = XO_(d9), XOg_FLDCW = 5, | ||
296 | XO_FNSTCW = XO_(d9), XOg_FNSTCW = 7 | ||
297 | } x86Op; | ||
298 | |||
299 | /* x86 opcode groups. */ | ||
300 | typedef uint32_t x86Group; | ||
301 | |||
302 | #define XG_(i8, i, g) ((x86Group)(((i8) << 16) + ((i) << 8) + (g))) | ||
303 | #define XG_ARITHi(g) XG_(XI_ARITHi8, XI_ARITHi, g) | ||
304 | #define XG_TOXOi(xg) ((x86Op)(0x000000fe + (((xg)<<16) & 0xff000000))) | ||
305 | #define XG_TOXOi8(xg) ((x86Op)(0x000000fe + (((xg)<<8) & 0xff000000))) | ||
306 | |||
307 | #define XO_ARITH(a) ((x86Op)(0x030000fe + ((a)<<27))) | ||
308 | #define XO_ARITHw(a) ((x86Op)(0x036600fd + ((a)<<27))) | ||
309 | |||
310 | typedef enum { | ||
311 | XOg_ADD, XOg_OR, XOg_ADC, XOg_SBB, XOg_AND, XOg_SUB, XOg_XOR, XOg_CMP, | ||
312 | XOg_X_IMUL | ||
313 | } x86Arith; | ||
314 | |||
315 | typedef enum { | ||
316 | XOg_ROL, XOg_ROR, XOg_RCL, XOg_RCR, XOg_SHL, XOg_SHR, XOg_SAL, XOg_SAR | ||
317 | } x86Shift; | ||
318 | |||
319 | typedef enum { | ||
320 | XOg_TEST, XOg_TEST_, XOg_NOT, XOg_NEG, XOg_MUL, XOg_IMUL, XOg_DIV, XOg_IDIV | ||
321 | } x86Group3; | ||
322 | |||
323 | typedef enum { | ||
324 | XOg_INC, XOg_DEC, XOg_CALL, XOg_CALLfar, XOg_JMP, XOg_JMPfar, XOg_PUSH | ||
325 | } x86Group5; | ||
326 | |||
327 | /* x86 condition codes. */ | ||
328 | typedef enum { | ||
329 | CC_O, CC_NO, CC_B, CC_NB, CC_E, CC_NE, CC_BE, CC_NBE, | ||
330 | CC_S, CC_NS, CC_P, CC_NP, CC_L, CC_NL, CC_LE, CC_NLE, | ||
331 | CC_C = CC_B, CC_NAE = CC_C, CC_NC = CC_NB, CC_AE = CC_NB, | ||
332 | CC_Z = CC_E, CC_NZ = CC_NE, CC_NA = CC_BE, CC_A = CC_NBE, | ||
333 | CC_PE = CC_P, CC_PO = CC_NP, CC_NGE = CC_L, CC_GE = CC_NL, | ||
334 | CC_NG = CC_LE, CC_G = CC_NLE | ||
335 | } x86CC; | ||
336 | |||
337 | #endif | ||