aboutsummaryrefslogtreecommitdiffstatshomepage
path: root/libraries/luajit-2.0/src/lj_target_arm.h
diff options
context:
space:
mode:
Diffstat (limited to 'libraries/luajit-2.0/src/lj_target_arm.h')
-rw-r--r--libraries/luajit-2.0/src/lj_target_arm.h210
1 files changed, 0 insertions, 210 deletions
diff --git a/libraries/luajit-2.0/src/lj_target_arm.h b/libraries/luajit-2.0/src/lj_target_arm.h
deleted file mode 100644
index b4b26d4..0000000
--- a/libraries/luajit-2.0/src/lj_target_arm.h
+++ /dev/null
@@ -1,210 +0,0 @@
1/*
2** Definitions for ARM CPUs.
3** Copyright (C) 2005-2011 Mike Pall. See Copyright Notice in luajit.h
4*/
5
6#ifndef _LJ_TARGET_ARM_H
7#define _LJ_TARGET_ARM_H
8
9/* -- Registers IDs ------------------------------------------------------- */
10
11#define GPRDEF(_) \
12 _(R0) _(R1) _(R2) _(R3) _(R4) _(R5) _(R6) _(R7) \
13 _(R8) _(R9) _(R10) _(R11) _(R12) _(SP) _(LR) _(PC)
14#if LJ_SOFTFP
15#define FPRDEF(_)
16#else
17#error "NYI: hard-float support for ARM"
18#endif
19#define VRIDDEF(_)
20
21#define RIDENUM(name) RID_##name,
22
23enum {
24 GPRDEF(RIDENUM) /* General-purpose registers (GPRs). */
25 FPRDEF(RIDENUM) /* Floating-point registers (FPRs). */
26 RID_MAX,
27 RID_TMP = RID_LR,
28
29 /* Calling conventions. */
30 RID_RET = RID_R0,
31 RID_RETLO = RID_R0,
32 RID_RETHI = RID_R1,
33 RID_FPRET = RID_R0,
34
35 /* These definitions must match with the *.dasc file(s): */
36 RID_BASE = RID_R9, /* Interpreter BASE. */
37 RID_LPC = RID_R6, /* Interpreter PC. */
38 RID_DISPATCH = RID_R7, /* Interpreter DISPATCH table. */
39 RID_LREG = RID_R8, /* Interpreter L. */
40
41 /* Register ranges [min, max) and number of registers. */
42 RID_MIN_GPR = RID_R0,
43 RID_MAX_GPR = RID_PC+1,
44 RID_MIN_FPR = RID_MAX_GPR,
45#if LJ_SOFTFP
46 RID_MAX_FPR = RID_MIN_FPR,
47#else
48#error "NYI: VFP support for ARM"
49#endif
50 RID_NUM_GPR = RID_MAX_GPR - RID_MIN_GPR,
51 RID_NUM_FPR = RID_MAX_FPR - RID_MIN_FPR
52};
53
54#define RID_NUM_KREF RID_NUM_GPR
55#define RID_MIN_KREF RID_R0
56
57/* -- Register sets ------------------------------------------------------- */
58
59/* Make use of all registers, except sp, lr and pc. */
60#define RSET_GPR (RSET_RANGE(RID_MIN_GPR, RID_R12+1))
61#define RSET_GPREVEN \
62 (RID2RSET(RID_R0)|RID2RSET(RID_R2)|RID2RSET(RID_R4)|RID2RSET(RID_R6)| \
63 RID2RSET(RID_R8)|RID2RSET(RID_R10))
64#define RSET_GPRODD \
65 (RID2RSET(RID_R1)|RID2RSET(RID_R3)|RID2RSET(RID_R5)|RID2RSET(RID_R7)| \
66 RID2RSET(RID_R9)|RID2RSET(RID_R11))
67#if LJ_SOFTFP
68#define RSET_FPR 0
69#define RSET_ALL RSET_GPR
70#else
71#error "NYI: VFP support for ARM"
72#endif
73#define RSET_INIT RSET_ALL
74
75/* ABI-specific register sets. lr is an implicit scratch register. */
76#define RSET_SCRATCH_GPR_ (RSET_RANGE(RID_R0, RID_R3+1)|RID2RSET(RID_R12))
77#ifdef __APPLE__
78#define RSET_SCRATCH_GPR (RSET_SCRATCH_GPR_|RID2RSET(RID_R9))
79#else
80#define RSET_SCRATCH_GPR RSET_SCRATCH_GPR_
81#endif
82#if LJ_SOFTFP
83#define RSET_SCRATCH_FPR 0
84#else
85#error "NYI: VFP support for ARM"
86#endif
87#define RSET_SCRATCH (RSET_SCRATCH_GPR|RSET_SCRATCH_FPR)
88#define REGARG_FIRSTGPR RID_R0
89#define REGARG_LASTGPR RID_R3
90#define REGARG_NUMGPR 4
91
92/* -- Spill slots --------------------------------------------------------- */
93
94/* Spill slots are 32 bit wide. An even/odd pair is used for FPRs.
95**
96** SPS_FIXED: Available fixed spill slots in interpreter frame.
97** This definition must match with the *.dasc file(s).
98**
99** SPS_FIRST: First spill slot for general use. Reserve min. two 32 bit slots.
100*/
101#define SPS_FIXED 2
102#define SPS_FIRST 2
103
104#define sps_scale(slot) (4 * (int32_t)(slot))
105#define sps_align(slot) (((slot) - SPS_FIXED + 1) & ~1)
106
107/* -- Exit state ---------------------------------------------------------- */
108
109/* This definition must match with the *.dasc file(s). */
110typedef struct {
111#if !LJ_SOFTFP
112 lua_Number fpr[RID_NUM_FPR]; /* Floating-point registers. */
113#endif
114 int32_t gpr[RID_NUM_GPR]; /* General-purpose registers. */
115 int32_t spill[256]; /* Spill slots. */
116} ExitState;
117
118/* PC after instruction that caused an exit. Used to find the trace number. */
119#define EXITSTATE_PCREG RID_PC
120/* Highest exit + 1 indicates stack check. */
121#define EXITSTATE_CHECKEXIT 1
122
123#define EXITSTUB_SPACING 4
124#define EXITSTUBS_PER_GROUP 32
125
126/* -- Instructions -------------------------------------------------------- */
127
128/* Instruction fields. */
129#define ARMF_CC(ai, cc) (((ai) ^ ARMI_CCAL) | ((cc) << 28))
130#define ARMF_N(r) ((r) << 16)
131#define ARMF_D(r) ((r) << 12)
132#define ARMF_S(r) ((r) << 8)
133#define ARMF_M(r) (r)
134#define ARMF_SH(sh, n) (((sh) << 5) | ((n) << 7))
135#define ARMF_RSH(sh, r) (0x10 | ((sh) << 5) | ARMF_S(r))
136
137typedef enum ARMIns {
138 ARMI_CCAL = 0xe0000000,
139 ARMI_S = 0x000100000,
140 ARMI_K12 = 0x02000000,
141 ARMI_KNEG = 0x00200000,
142 ARMI_LS_W = 0x00200000,
143 ARMI_LS_U = 0x00800000,
144 ARMI_LS_P = 0x01000000,
145 ARMI_LS_R = 0x02000000,
146 ARMI_LSX_I = 0x00400000,
147
148 ARMI_AND = 0xe0000000,
149 ARMI_EOR = 0xe0200000,
150 ARMI_SUB = 0xe0400000,
151 ARMI_RSB = 0xe0600000,
152 ARMI_ADD = 0xe0800000,
153 ARMI_ADC = 0xe0a00000,
154 ARMI_SBC = 0xe0c00000,
155 ARMI_RSC = 0xe0e00000,
156 ARMI_TST = 0xe1100000,
157 ARMI_TEQ = 0xe1300000,
158 ARMI_CMP = 0xe1500000,
159 ARMI_CMN = 0xe1700000,
160 ARMI_ORR = 0xe1800000,
161 ARMI_MOV = 0xe1a00000,
162 ARMI_BIC = 0xe1c00000,
163 ARMI_MVN = 0xe1e00000,
164
165 ARMI_NOP = 0xe1a00000,
166
167 ARMI_MUL = 0xe0000090,
168 ARMI_SMULL = 0xe0c00090,
169
170 ARMI_LDR = 0xe4100000,
171 ARMI_LDRB = 0xe4500000,
172 ARMI_LDRH = 0xe01000b0,
173 ARMI_LDRSB = 0xe01000d0,
174 ARMI_LDRSH = 0xe01000f0,
175 ARMI_LDRD = 0xe00000d0,
176 ARMI_STR = 0xe4000000,
177 ARMI_STRB = 0xe4400000,
178 ARMI_STRH = 0xe00000b0,
179 ARMI_STRD = 0xe00000f0,
180 ARMI_PUSH = 0xe92d0000,
181
182 ARMI_B = 0xea000000,
183 ARMI_BL = 0xeb000000,
184 ARMI_BLX = 0xfa000000,
185 ARMI_BLXr = 0xe12fff30,
186
187 /* ARMv6 */
188 ARMI_REV = 0xe6bf0f30,
189 ARMI_SXTB = 0xe6af0070,
190 ARMI_SXTH = 0xe6bf0070,
191 ARMI_UXTB = 0xe6ef0070,
192 ARMI_UXTH = 0xe6ff0070,
193
194 /* ARMv6T2 */
195 ARMI_MOVW = 0xe3000000,
196 ARMI_MOVT = 0xe3400000,
197} ARMIns;
198
199typedef enum ARMShift {
200 ARMSH_LSL, ARMSH_LSR, ARMSH_ASR, ARMSH_ROR
201} ARMShift;
202
203/* ARM condition codes. */
204typedef enum ARMCC {
205 CC_EQ, CC_NE, CC_CS, CC_CC, CC_MI, CC_PL, CC_VS, CC_VC,
206 CC_HI, CC_LS, CC_GE, CC_LT, CC_GT, CC_LE, CC_AL,
207 CC_HS = CC_CS, CC_LO = CC_CC
208} ARMCC;
209
210#endif
generated by cgit v1.1 at 2024-07-01 03:58:51 +0000